In fabricating microelectronic semiconductor devices and the like on a semiconductor wafer (substrate or chip), e.g., of silicon, to form an integrated circuit (IC), etc., various metal layers and insulation layers are provided in selective sequence on the wafer. To maximize device component integration in the available wafer area to fit more components in the same area, increased IC miniaturization is utilized. Reduced pitch dimensions are used for denser packing of components per very large scale integration (VLSI) technique, e.g., at sub-micron dimensions, i.e., below 1 micron or 1,000 nanometers (nm) or 10,000 angstroms (A).
A CMP process is known for providing a damascene (inlaid) pattern, i.e., an arrangement of closely spaced apart individual metal lines, e.g., of copper (Cu), unconnected to each other and disposed in a like arrangement of closely spaced apart trenches, in an insulation layer, e.g., an oxide layer such as of silicon dioxide (SiO.sub.2), in the IC fabrication of a semiconductor wafer, e.g., of silicon (Si).
A liner layer forming an adhesion promoting diffusion barrier is optionally disposed between a lower insulation layer such as an oxide layer containing the trenches and an upper metal layer used to provide the individual metal lines in the trenches. When the liner layer is absent, the known CMP process is a one-phase process comprising a one-step metal layer CMP process, and when the liner layer is present, the known CMP process is a two-phase process comprising a one-step metal layer CMP process as a first phase, e.g., of about 210 seconds (3.5 minutes) polishing time, and a liner layer removing CMP process as second phase, e.g., of about 90 seconds (1.5 minutes) polishing time, for a total process (polishing) time of about 300 seconds (5 minutes).
For instance, the wafer, e.g., a circular disc of about 8 inches (200 mm) diameter, has a copper layer disposed on the oxide layer so as to provide an arrangement of wide metal lines, i.e., metal lines having a width of at least about 2 microns, such as about 2-100 microns, in the arrangement of trenches of the oxide layer. The wafer is polished in conventional manner by a rotating polishing pad, e.g., at about 20-100 rpm, such as about 55 rpm. The first phase CMP is effected under a polishing pressure downforce of about 4.5 psi for a total first phase CMP process (polishing) time of about 210 seconds (3.5 minutes), to an extent for providing the wide metal lines as individual lines unconnected to each other, i.e., by the metal (copper) of the copper metal layer.
Specifically, sufficient overpolishing is used to assure complete removal of the metal layer portion which overlies the metal lines and also the metal layer portion which is disposed over the adjacent field areas of the oxide layer outwardly of the metal lines. This overpolishing assures that the individual metal lines are no longer connected to each other through the overlying metal layer portion.
However, the so polished wafer suffers from pronounced attendant dishing in the damascene pattern area containing the metal line arrangement in the trench arrangement. Dishing is the formation of a concave depression, e.g., in the arrangement of metal lines in the arrangement of trenches, which occurs during CMP with the rotating polishing pad, and becomes increasingly pronounced as polishing pressure downforce increases, which at the same time increases the process speed (polishing rate).
On the one hand, copper CMP is one of the most costly processes in semiconductor fabrication. Any polishing rate increase (polishing time reduction) would thus be desirable to improve the competitiveness of this CMP process. On the other hand, dishing, which generally increases with increasing polishing pressure, is an important process parameter that directly controls the sheet resistance (RS) performance of each individual wide metal line. In this regard, RS is the quotient of the resistivity of the metal material divided by the metal line thickness (height) and is a measure of the amount of current the line can carry. Of course, such metal line height decreases as the dishing depth increases, and the smaller the metal line cross sectional area, the smaller the current the line can carry.
It is desirable to have a CMP process for forming an arrangement of closely spaced apart metal lines, especially wide metal lines, e.g., of copper, as individual metal lines in a like arrangement of trenches in an insulation layer of a semiconductor wafer, which provides an increase in polishing rate (shorter polishing time) without an increase in dishing or a reduction in dishing while retaining a high polishing rate.